The invention relates to a cache memory control system.
The cache memory (often called a buffer memory) has widely been used in a large scale computer with a view to reduction of an effective access time to a main memory with a large memory capacity but with a long access time. The cache memory has recently been used frequently in the filed of a large scale minicomputer (called a mega minicomputer with a large memory capacity).
As shown in FIG. 1 illustrating a relationship between a main memory and a cache memory, the unitary data which is called a block is transferred between a main memory 102 and a cache memory 103. When a central processing unit (CPU) 101 requires data, necessary data is read out from a main memory 102 and then is stored in the cache memory 103. In this manner, an effective access time is reduced. In designing such a data processing system, the following items must be taken into consideration.
1. To optimize a block size including unnecessary data:
The ratio of the necessary data contained in a block to the unnecessary data contained therein must be minimized for securing the effective memory access.
2. To optimize the number of blocks required for CPU:
Since the memory capacity of the cache memory 103 is restrictive, the number of blocks to be stored in the cache memory 103 must be optimized for the same purpose.
3. When a new block is loaded into the cache memory 103, the optimum number of blocks must be pulled out from the cache memory 103.
4. The nature of a program:
In making an access to memory, addresses must be optimumly selected. A nature of a program that a certain routine must be executed repeatedly, for example, influences largely a frequency of block transfer.
Many attempts have been made to fully satisfy the just-mentioned items. One of them is disclosed in Japan Examined Patent Application No. 4011/43 of Showa (1968) entitled "Information Memory Apparatus" filed by IBM. The IBM patent uses a buffer memory between a main memory and CPU for storing a copy of the contents in the main memory. Another example is disclosed in Japan Examined Patent Application No. 3445/48 of Showa (1973) filed by the same applicant, in which describes the improvement of a data processing system with a memory hierarchy including a high speed buffer memory.
Those conventional apparatuses, however, still suffer from the following drawbacks; (a) The performance might be improved but the cost/performance is poor, (b) The economical improvement conversely deteriorates the system performance, and (c) The access method to the main memory of CUP (i.e. the nature of a program) is not optimized.